Differences

This shows you the differences between two versions of the page.

--- make [2021/03/22 09:29] – created utedass
+++ make [2022/09/12 00:30] (current) – external edit 127.0.0.1
@@ Line 1: / Line 1: @@
 ====== Overview ======
 [[https://www.gnu.org/software/make/manual/html_node/index.html|HTML Manual]]
+<code bash>
+# Print without running
+$ make --just-print
+or
+$ make -n
+# Print lot of stuff
+$ make --print-data-base
+</code>
+====== Magic symbols ======
+[[https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables|Automatic variables]]
+| $@ | Target |
+| $%%^%% | All prerequisites (excluding duplicates) |
+| $+ | All prerequisites (including duplicates) |
+| $? | All prerequisites newer than target |
+| $< | First prerequisite |
+| $(@D) | Directory part of target with trailing slash |
+| $(@F) | File part of target without directory path |
+| $* | The stem of the target match in implicit rules |
 ====== Examples ======
@@ Line 11: / Line 33: @@
 # Define a bunch of variables
 CC=gcc
-CFLAGS=-std=c99 -Wall -Wextra -pedantic -O3 -I utils/
+CFLAGS=-std=c99 -Wall -Wextra -pedantic -O3 -I utils
 DEPS=main.o cbuf.o event_system.o fsm.o
 OUTFILE=main.exe
@@ Line 26: / Line 48: @@
 	# $< is all the dependencies
 	$(CC) -o $@ $< $(CFLAGS)
+	@echo "This command line is not echoed thanks to @. The output to stdout is, however, printed"
 # This rule matches targets ending with .o, and it depends on the same filename ending with .c
@@ Line 36: / Line 59: @@
 </code>
+Evaluation time of variables
+<code make>
+# This will populate TEXTEN with the output from the shell command ls
+TEXTEN = $(lsoutput)      # TEXTEN will contain $(lsouput) and will be evaluated when used
+TEXTEN2 := $(lsoutput)    # TEXTEN2 will contain the evaluated $(lsoutput), which is blank at this line
+lsoutput = $(shell ls)    # Hereafter $(lsoutput) will evaluate to what ls returns
+</code>
+<code make>
+# Substitutions when referencing variables, only the ending is substituted
+SOURCES = a.c b.c c.c
+OBJECTS = $(SOURCES:c=o)
+</code>
+<code make>
+# A make file that compiles all c files and places object files
+# in the same tree-structure that the sources were found
+CC = gcc
+CFLAGS = -std=c99 -Wall -Wextra -pedantic -O0 -I. -I utils -I protocol -I command -I driver
+OUTFILE = main.exe
+OBJDIR  := build/objects
+SOURCES := $(shell find * -type f -name "*.c")
+OBJECTS := $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o))
+run: $(OUTFILE)
+	@echo "";
+	@./$(OUTFILE)
+$(OUTFILE): $(OBJECTS)
+	$(CC) -o $@ $^ $(CFLAGS)
+$(OBJECTS): $(OBJDIR)/%.o: %.c
+	mkdir -p $(@D)
+	$(CC) -c -o $@ $^ $(CFLAGS)
+.PHONY: clean
+clean:
+	@rm -f $(OUTFILE) *.mk *.o *.pp *.s listing.txt
+	@rm -rf $(OBJDIR)
+</code>