make
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Overview
Examples
# This is a comment # And this is\ a multi line comment # Define a bunch of variables CC=gcc CFLAGS=-std=c99 -Wall -Wextra -pedantic -O3 -I utils DEPS=main.o cbuf.o event_system.o fsm.o OUTFILE=main.exe # VPATH tells make to search the following directories for targets and dependencies. Separated with : VPATH = utils:../header:src # A rule with any of the following names are always run, even if a file with that name already exists .PHONY: clean run pre remake asm # A rule that describes how to generate $(OUTFILE), after all of the depencies $(DEPS) has been made $(OUTFILE): $(DEPS) # $@ is the target # $< is all the dependencies $(CC) -o $@ $< $(CFLAGS) @echo "This command line is not echoed thanks to @. The output to stdout is, however, printed" # This rule matches targets ending with .o, and it depends on the same filename ending with .c %.o: %.c $(CC) -c -o $@ $< $(CFLAGS) # A rule that doesn't correspond to a file, thanks to .PHONY, but can always be run clean: @rm -f $(OUTFILE) *.mk *.o *.pp *.s listing.txt
Evaluation time of variables
# This will populate TEXTEN with the output from the shell command ls TEXTEN = $(lsoutput) # TEXTEN will contain $(lsouput) and will be evaluated when used TEXTEN2 := $(lsoutput) # TEXTEN2 will contain the evaluated $(lsoutput), which is blank at this line lsoutput = $(shell ls) # Hereafter $(lsoutput) will evaluate to what ls returns
make.1616407150.txt.gz · Last modified: 2022/09/12 00:30 (external edit)
