Synario VHDL Manual

VHDL Verilog Cosimulation

library ieee;
use ieee.std_logic_1164.all; -- std_logic_vector
use ieee.numeric_std.all; -- signed and unsigned
 
-- numbers, math operations allowed
signal my_int : integer; -- 32 bit 2-complement
signal my_uint : unsigned (7 downto 0);
signal my_sint : signed (7 downto 0);
 
-- loose bits, math operations not allowed
signal my_bits : std_logic_vector (7 downto 0);
 
-- conversions between integers
my_uint <= to_unsigned(my_int, 8); -- Must specify bit length
my_sint <= to_signed(my_int, 8);
 
my_int <= to_integer(my_uint);
my_int <= to_integer(my_sint);
 
-- casts between binary representations, number of bits must match
my_uint <= unsigned(my_sint);
my_uint <= unsigned(my_bits);
 
my_sint <= signed(my_uint);
my_sint <= signed(my_bits);
 
my_bits <= std_logic_vector(my_uint);
my_bits <= std_logic_vector(my_sint);

-- after statements can be chained in the concurrent scope as such:
reset <= '0', '1' after 20 us, '0' after 40 us, '1' after 300 us, '0' after 320 us;