Jegatron

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====== VHDL ======
[[https://opencores.org/|opencores]] -- Mostly verilog? Might find something useful

===== Things is should write down =====

  * Math-functions for determining bit width (IEEE.math_real.all)
  * Generic notation
  * natural and conversion to integer and real
  * Defining functions
  * Entity instantiation [[https://stackoverflow.com/questions/36229368/component-instantiation-vs-entity-instantiation-in-vhdl|Stack overflow]]
  * State machines using type
  * Some simulation specific stuff like after 3ps, assert and until rising_edge(clk)
  * High impedance value of std_logic ('Z'), only for ports
  * Naming conventions once I have settled for one
  * Generate statement
  * Immediate values syntax

===== Conversions =====

<code vhdl>
library ieee;
use ieee.std_logic_1164.all; -- std_logic_vector
use ieee.numeric_std.all; -- signed and unsigned

-- numbers, math operations allowed
signal my_int : integer; -- 32 bit 2-complement
signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not
signal my_uint : unsigned (7 downto 0);
signal my_sint : signed (7 downto 0) := x"0a"; -- Default values might not synthesize, depends on target

-- loose bits, math operations not allowed
signal my_bit : std_logid;
signal my_bits : std_logic_vector (7 downto 0);

-- Integer assignements
my_int <= 1337; -- Decimal
my_int <= 16#beef#; -- Hex (base 16)
my_int <= 2#101010; -- Binary (base 2)

-- std_logic assignement
my_bit <= '0';

-- Assignments to std_logic_vector (also works on signed and unsigned)
-- All assignments must match in width
my_bits <= (others => '0'); -- Set all bits to '0'
my_bits(3 downto 0) <= (others => '1'); -- Set lowest 4 bits to '1'
my_bits <= "10101011"; -- Set with bit array
my_bits <= x"ab"; -- Set with hex
my_bits <= '1' & '0' & "10" & x"b"; -- Concatenate different notations

-- conversions between integers
my_uint <= to_unsigned(my_int, 8); -- Must specify bit length
my_sint <= to_signed(my_int, 8);

my_int <= to_integer(my_uint);
my_int <= to_integer(my_sint);

-- casts between binary representations, lenght must match
my_uint <= unsigned(my_sint);
my_uint <= unsigned(my_bits);

my_sint <= signed(my_uint);
my_sint <= signed(my_bits);

my_bits <= std_logic_vector(my_uint);
my_bits <= std_logic_vector(my_sint);

-- From ASCII code value
my_ascii_code <= std_logic_vector(to_unsigned(character'pos('A'), my_ascii_code'length));

-- From number immediate values to std_logic_vector
my_immediate_hex <= std_logic_vector(to_unsigned(16#150#, my_immediate_hex'length));
my_immediate_dec <= std_logic_vector(to_unsigned(10#150#, my_immediate_dec'length));

</code>


<code vhdl>
-- Char to unsigned
tx_char <= to_unsigned(character'pos('a'), 8);
</code>

===== Textio =====
Can be used in simulation.

<code vhdl>
use std.textion.all;

-- Further down...
  process is
    variable l : line;
  begin
    write (l, String'("Hello world!"));
    writeline (output, l);
    wait;
  end process;
</code>

===== Other things =====

<code vhdl>
report "this is a message"; -- severity note
-- or:
report "this is a serious message" severity warning; -- Possible values: note, warning, error, failure
</code>