fpga:vhdl
Differences
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| Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
| fpga:vhdl [2025/06/13 07:40] – utedass | fpga:vhdl [2026/09/28 09:17] (current) – [Other things] utedass | ||
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| Line 27: | Line 27: | ||
| signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not | signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not | ||
| signal my_uint : unsigned (7 downto 0); | signal my_uint : unsigned (7 downto 0); | ||
| - | signal my_sint : signed (7 downto 0); | + | signal my_sint : signed (7 downto 0) := x" |
| -- loose bits, math operations not allowed | -- loose bits, math operations not allowed | ||
| Line 100: | Line 100: | ||
| <code vhdl> | <code vhdl> | ||
| - | report "this is a message"; | + | report "this is a message"; |
| -- or: | -- or: | ||
| report "this is a serious message" | report "this is a serious message" | ||
| </ | </ | ||
fpga/vhdl.1749800443.txt.gz · Last modified: 2025/06/13 07:40 by utedass