fpga:vhdl
Differences
This shows you the differences between two versions of the page.
| Both sides previous revisionPrevious revision | |||
| fpga:vhdl [2025/06/13 07:40] – utedass | fpga:vhdl [2025/06/13 12:33] (current) – utedass | ||
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| signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not | signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not | ||
| signal my_uint : unsigned (7 downto 0); | signal my_uint : unsigned (7 downto 0); | ||
| - | signal my_sint : signed (7 downto 0); | + | signal my_sint : signed (7 downto 0) := x" |
| -- loose bits, math operations not allowed | -- loose bits, math operations not allowed | ||
fpga/vhdl.1749800443.txt.gz · Last modified: 2025/06/13 07:40 by utedass