Differences

This shows you the differences between two versions of the page.

--- fpga:vhdl [2025/06/13 07:32] – utedass
+++ fpga:vhdl [2025/06/13 12:33] (current) – utedass
@@ Line 25: / Line 25: @@
 -- numbers, math operations allowed
 signal my_int : integer; -- 32 bit 2-complement
+signal my_int_ranged : integer -1 to 23; -- Limited range. Simulator might enforce, synthesiser might not
 signal my_uint : unsigned (7 downto 0);
-signal my_sint : signed (7 downto 0);
+signal my_sint : signed (7 downto 0) := x"0a"; -- Default values might not synthesize, depends on target
+-- loose bits, math operations not allowed
+signal my_bit : std_logid;
+signal my_bits : std_logic_vector (7 downto 0);
+-- Integer assignements
 my_int <= 1337; -- Decimal
 my_int <= 16#beef#; -- Hex (base 16)
 my_int <= 2#101010; -- Binary (base 2)
--- loose bits, math operations not allowed
+-- std_logic assignement
-signal my_bits : std_logic_vector (7 downto 0);
+my_bit <= '0';
+-- Assignments to std_logic_vector (also works on signed and unsigned)
+-- All assignments must match in width
+my_bits <= (others => '0'); -- Set all bits to '0'
+my_bits(3 downto 0) <= (others => '1'); -- Set lowest 4 bits to '1'
+my_bits <= "10101011"; -- Set with bit array
+my_bits <= x"ab"; -- Set with hex
+my_bits <= '1' & '0' & "10" & x"b"; -- Concatenate different notations
 -- conversions between integers
@@ Line 42: / Line 56: @@
 my_int <= to_integer(my_sint);
--- casts between binary representations, number of bits must match
+-- casts between binary representations, lenght must match
 my_uint <= unsigned(my_sint);
 my_uint <= unsigned(my_bits);
@@ Line 58: / Line 72: @@
 my_immediate_hex <= std_logic_vector(to_unsigned(16#150#, my_immediate_hex'length));
 my_immediate_dec <= std_logic_vector(to_unsigned(10#150#, my_immediate_dec'length));
--- std_logic constant assignement
-my_bit <= '0';
--- std_logic_vector constant assignment
-my_bits <= x"ab"; -- Using hex string
-my_bits <= "10010110"; -- Using bit string
 </code>