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arm:atsamc21

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arm:atsamc21 [2021/05/26 09:55] – [MCLK, Main Clock system] utedassarm:atsamc21 [2022/09/12 00:30] (current) – external edit 127.0.0.1
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 ===== Clocks and synchronisation ===== ===== Clocks and synchronisation =====
 At startup the clock is configured to 4 MHz. At startup the clock is configured to 4 MHz.
 +
 +The initial clock setup is described in chapter 15.7 and chapter 12.
  
 All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly. All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly.
Line 55: Line 57:
  
 Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems. Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems.
- 
-The initial clock setup is described in chapter 15.7 and chapter 12. 
  
 Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6. Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6.
  
 ==== MCLK, Main Clock system ==== ==== MCLK, Main Clock system ====
-Three equal examples for enabling the synchronized bus clock for the timer TC0.+Three equivalent examples for enabling the synchronized bus clock for the timer TC0.
 <code c> <code c>
 MCLK->APBCMASK.bit.TC0_ = 1; MCLK->APBCMASK.bit.TC0_ = 1;
Line 86: Line 86:
 Example of how to hook up TC0 to Generator 2 Example of how to hook up TC0 to Generator 2
 <code c> <code c>
-GCLK.GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); +GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); 
-GCLK.PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);+GCLK->PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);
 </code> </code>
 ===== Step-by-step ===== ===== Step-by-step =====
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 </code> </code>
  
 +====== CAN Bus Peripheral ======
 +
 +[[https://electronics.stackexchange.com/questions/478864/atsamc21-can-configuration-nominal-bit-timing-vs-data-bit-timing-time-qua|StackOverflow]] -- Undocumented baud calculation
 +
 +
 +''total_tq = sync_seg_tq + (phase_seg1_tq+1) + (phase_seg2_tq+1)'' where ''sync_seg_tq == 1'' always.
 ====== Programming ====== ====== Programming ======
 Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]] Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]]
arm/atsamc21.1622022939.txt.gz · Last modified: 2022/09/12 00:30 (external edit)
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