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arm:atsamc21 [2021/01/05 14:03] – [GCLK, Generic Clock system] utedassarm:atsamc21 [2022/09/12 00:30] (current) – external edit 127.0.0.1
Line 45: Line 45:
 ===== Clocks and synchronisation ===== ===== Clocks and synchronisation =====
 At startup the clock is configured to 4 MHz. At startup the clock is configured to 4 MHz.
 +
 +The initial clock setup is described in chapter 15.7 and chapter 12.
  
 All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly. All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly.
Line 55: Line 57:
  
 Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems. Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems.
- 
-The initial clock setup is described in chapter 15.7 and chapter 12. 
  
 Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6. Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6.
  
 ==== MCLK, Main Clock system ==== ==== MCLK, Main Clock system ====
-Examples for enabling the synchronized bus clock for the timer TC0.+Three equivalent examples for enabling the synchronized bus clock for the timer TC0.
 <code c> <code c>
 MCLK->APBCMASK.bit.TC0_ = 1; MCLK->APBCMASK.bit.TC0_ = 1;
Line 86: Line 86:
 Example of how to hook up TC0 to Generator 2 Example of how to hook up TC0 to Generator 2
 <code c> <code c>
-GCLK.GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); +GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); 
-GCLK.PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);+GCLK->PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);
 </code> </code>
 ===== Step-by-step ===== ===== Step-by-step =====
Line 216: Line 216:
 </code> </code>
  
 +====== CAN Bus Peripheral ======
 +
 +[[https://electronics.stackexchange.com/questions/478864/atsamc21-can-configuration-nominal-bit-timing-vs-data-bit-timing-time-qua|StackOverflow]] -- Undocumented baud calculation
 +
 +
 +''total_tq = sync_seg_tq + (phase_seg1_tq+1) + (phase_seg2_tq+1)'' where ''sync_seg_tq == 1'' always.
 ====== Programming ====== ====== Programming ======
 Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]] Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]]
Line 237: Line 243:
 <code batch> <code batch>
 $ arm-none-eabi-gdb main.elf --eval-command="target remote localhost:3333" $ arm-none-eabi-gdb main.elf --eval-command="target remote localhost:3333"
 +</code>
 +
 +
 +A file named ''openocd.cfg'' in the same folder as openocd is started in is supposed to be loaded automatically. But sometimes this doesn't seem to work. In this case run ''openocd -f script_file.fcg''
 +<code tcl>
 +# Filename: openocd.cfg
 +# or envoke with openocd -f filename.cfg
 +
 +# Explicit debugger and target config files
 +#source [find interface/cmsis-dap.cfg]
 +#source [find target/at91samdXX.cfg]
 +
 +# Readily available config instead of the explicit setup above
 +source [find board/atmel_samc21_xplained_pro.cfg]
 +
 +# Some of the sleep commands seems necessary, otherwise the MCU doesnt seem to react properly
 +
 +# Set to known state
 +init
 +reset init
 +sleep 25
 +
 +# Erase flash
 +at91samd chip-erase
 +sleep 25
 +
 +# Write firmware
 +flash write_bank 0 flash_image.bin 0
 +sleep 25
 +
 +# Reset MCU
 +reset
 +sleep 25
 +
 +# Shut down openocd server
 +shutdown
 +sleep 25
 </code> </code>
 ====== Getting started ====== ====== Getting started ======
arm/atsamc21.1609855417.txt.gz · Last modified: 2022/09/12 00:30 (external edit)
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