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arm:atsamc21 [2020/08/25 12:29] – [Clocks and synchronisation] utedassarm:atsamc21 [2022/09/12 00:30] (current) – external edit 127.0.0.1
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 ====== SAMC21 Xplained Pro ====== ====== SAMC21 Xplained Pro ======
 +[[http://ww1.microchip.com/downloads/en/devicedoc/Atmel-42460-SAM-C21-Xplained-Pro_User-Guide.pdf|User guide]] [[https://www.microchip.com/DevelopmentTools/ProductDetails/PartNO/ATSAMC21-XPRO| Product page]]
 +
 Based on ATSAMC21J18A Based on ATSAMC21J18A
 +
  
 The SAM21 Xplained Pro development board has some peripherals attached: The SAM21 Xplained Pro development board has some peripherals attached:
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 ====== Using peripherals ====== ====== Using peripherals ======
 +[[https://microchipdeveloper.com/32arm:differences-among-arm-cortex-families|Developer portal]]
  
 ===== Clocks and synchronisation ===== ===== Clocks and synchronisation =====
 At startup the clock is configured to 4 MHz. At startup the clock is configured to 4 MHz.
 +
 +The initial clock setup is described in chapter 15.7 and chapter 12.
  
 All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly. All peripherals interfaces two different clock-domains; their individual General Clock source, and the synchronized APB, or AHB, clock that is interfaced by the CPU. Both of these clock sources need to be configured properly.
  
-The General Clock source is configured by a ''GCLK_XXXX_CORE'' register, see chapter 16.8.4 table 16-9 for the register mappings. A peripheral can require several General Clock sources.+A General Clock source is configured by a ''GCLK_XXXX_CORE'' register, see chapter 16.8.4 table 16-9 for the register mappings. A peripheral can require several General Clock sources.
  
 The synchronized clock is controlled by a bit mask in the Main Clock system, MCLK chapter 17. To quickly find the relevant registers, refer to the peripherals chapter x.5.3 Product Dependencies - Clocks. The synchronized clock is controlled by a bit mask in the Main Clock system, MCLK chapter 17. To quickly find the relevant registers, refer to the peripherals chapter x.5.3 Product Dependencies - Clocks.
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 Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems. Each core register has its own synchronization mechanism, which makes it possible to write to different core registers consecutively without problems.
- 
-The initial clock setup is described in chapter 15.7 and chapter 12. 
  
 Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6. Maximum clock frequencies for different parts of the controller can be found in table 45-8 in chapter 45.6.
  
 ==== MCLK, Main Clock system ==== ==== MCLK, Main Clock system ====
-Examples for enabling the synchronized bus clock for the timer TC0.+Three equivalent examples for enabling the synchronized bus clock for the timer TC0.
 <code c> <code c>
 MCLK->APBCMASK.bit.TC0_ = 1; MCLK->APBCMASK.bit.TC0_ = 1;
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 </code> </code>
 ==== GCLK, Generic Clock system ==== ==== GCLK, Generic Clock system ====
-There are nine Generic Clock Generators. The Generator 0 is dedicated to source the Main Clock system.+There are nine Generic Clock Generators. Generator 0 is dedicated to source the Main Clock system and is enabled by default.
  
-Each Generic Clock Generator can be sourced from one of several clock sources. These Generators all have their individual clock divider. Generator 1 can be used as clock source for other generators.+Each Generic Clock Generator can be sourced from one of several clock sources. These Generators all have their individual clock divider. Generator 1 is the only generator that can be used as clock source for other generators.
  
 There are several Peripheral Channels. The number is dependent on the number of peripherals in the chip. Maximum 64. There are 41 in the ATSAMC21J18A. There are several Peripheral Channels. The number is dependent on the number of peripherals in the chip. Maximum 64. There are 41 in the ATSAMC21J18A.
  
-Each Peripheral Channel can be sourced from any one of the Generic Clock Generators. Each Peripheral Channel is connected to one peripheral. The Peripheral Channel consists of a MUX and a clock gate.+Each Peripheral Channel can be sourced from any one of the Generic Clock Generators. Each Peripheral Channel is harwired to one peripheral. The Peripheral Channel consists of a MUX and a clock gate.
  
-The ''GENCTRL[x]'' must be written to as one 32-bit register, because of the synchronization mechanism. +The ''GENCTRL[x]'' must be written to as one whole 32-bit register, because of the synchronization mechanism. 
  
 Example of how to hook up TC0 to Generator 2 Example of how to hook up TC0 to Generator 2
 <code c> <code c>
-GCLK.GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); +GCLK->GENCTRL[2].reg = GCLK_GENCTRL_DIV(100) | GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC(GCLK_GENCTRL_SRC_OSC48M_Val); 
-GCLK.PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);+GCLK->PCHCTRL[TC0_GCLK_ID].bit.CHEN = GCLK_PCHCTRL_CHEN | GCLK_PCHCTRL_GEN(GCLK_PCHCTRL_GEN_GCLK2_Val);
 </code> </code>
 ===== Step-by-step ===== ===== Step-by-step =====
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 ====== PORT peripheral ====== ====== PORT peripheral ======
 +[[arm:atsamc21:pinout|ATSAMC21 pinout]]
 +
 Only requires APB clock, ''CLK_PORT_APB'', to be interfaced. This is enabled by default at reset. There is no Generic Clock for the PORT peripheral. Only requires APB clock, ''CLK_PORT_APB'', to be interfaced. This is enabled by default at reset. There is no Generic Clock for the PORT peripheral.
  
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  now = TC0->COUNT16.COUNT.reg;  now = TC0->COUNT16.COUNT.reg;
  
- if(now-last_time > 32768) // Should be 1 sek+ if((uint16_t)(now - last_time) > 32768u) // Should be 1 sek
  {  {
  PORT->Group[0].OUTTGL.reg = PORT_PA15;  PORT->Group[0].OUTTGL.reg = PORT_PA15;
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 </code> </code>
  
 +====== CAN Bus Peripheral ======
 +
 +[[https://electronics.stackexchange.com/questions/478864/atsamc21-can-configuration-nominal-bit-timing-vs-data-bit-timing-time-qua|StackOverflow]] -- Undocumented baud calculation
 +
 +
 +''total_tq = sync_seg_tq + (phase_seg1_tq+1) + (phase_seg2_tq+1)'' where ''sync_seg_tq == 1'' always.
 ====== Programming ====== ====== Programming ======
 Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]] Good place: [[https://microchipdeveloper.com/32arm:sam-bare-metal-c-programming]]
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 </code> </code>
  
 +<code batch>
 +$ telnet localhost 4444
 +> reset halt
 +> at91samd chip-erase
 +> flash write_bank 0 main.bin 0
 +</code>
 +
 +<code batch>
 +$ arm-none-eabi-gdb main.elf --eval-command="target remote localhost:3333"
 +</code>
 +
 +
 +A file named ''openocd.cfg'' in the same folder as openocd is started in is supposed to be loaded automatically. But sometimes this doesn't seem to work. In this case run ''openocd -f script_file.fcg''
 +<code tcl>
 +# Filename: openocd.cfg
 +# or envoke with openocd -f filename.cfg
 +
 +# Explicit debugger and target config files
 +#source [find interface/cmsis-dap.cfg]
 +#source [find target/at91samdXX.cfg]
 +
 +# Readily available config instead of the explicit setup above
 +source [find board/atmel_samc21_xplained_pro.cfg]
 +
 +# Some of the sleep commands seems necessary, otherwise the MCU doesnt seem to react properly
 +
 +# Set to known state
 +init
 +reset init
 +sleep 25
 +
 +# Erase flash
 +at91samd chip-erase
 +sleep 25
 +
 +# Write firmware
 +flash write_bank 0 flash_image.bin 0
 +sleep 25
 +
 +# Reset MCU
 +reset
 +sleep 25
 +
 +# Shut down openocd server
 +shutdown
 +sleep 25
 +</code>
 ====== Getting started ====== ====== Getting started ======
 ===== Download and install Atmel Studio ===== ===== Download and install Atmel Studio =====
arm/atsamc21.1598358542.txt.gz · Last modified: 2022/09/12 00:30 (external edit)
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